Cosmic rays, also known as radiation, cosmic particles, ionized particles or alpha particles, are actually electrons, protons, heavy ions or atomic nuclei that travel through space with very high energy. Cosmic rays can penetrate the metal skin of a spacecraft and pass through electronic devices inside the spacecraft. When a cosmic particle penetrates an electronic circuit element, a small amount of electric charge may be deposited in the circuit element. In many integrated circuits, charge represents a logic state. If a radiation hit occurs within an integrated circuit, this deposited charge can change the logic state of the integrated circuit at the location where the radiation hit occurred. This phenomenon has been known to cause errors in electronic memories of equipment such as artificial satellites.
The occurrence of an error within electronic circuitry as a result of a cosmic particle strike is called a single event upset or SEU. An SEU can occur in an integrated circuit when radiation hits a susceptible point in the integrated circuit. Many integrated circuits include latches and flip flop elements. A cosmic ray strike to a latch or flip flop can result in the deposit of a transient charge in the latch or flip flop and cause the latch or flip flop to change state. The state of the latch or flip flop is used as a form of stored information. When a transient phenomenon causes a latch or a flip flop to change state, the result can be an error in the stored information. Depending upon the circuit, it is possible that the error is not corrected. Although only a temporary disturbance occurs at the location of the cosmic particle strike, the error can be made permanent through feedback. In addition, trends within integrated circuits to require increasingly smaller features, have produced smaller latches and flip flops. As a result, the relative size and effect of cosmic particles are increased with respect to smaller latches and flip flop elements. Therefore, latches and flip flop elements are more vulnerable to cosmic particle hits due to the smaller circuit geometries of present day integrated circuits. As a result, SEU is easily observed in latches, flip flops and integrated circuits.
It has been determined that an SEU can also occur when a cosmic ray strikes a combinational logic block. Combinational logic is a term used to describe logic circuits that are used to create a data bit, or result, that will be stored in a latch or a flip flop. The process of storing data in a latch or a flip flop is controlled by a clock signal. Proper functioning of any conventional latch or flip flop requires an input signal that remains stable and in a correct state for a certain period of time before and after a critical transition period, or edge of the clock signal. If a voltage disturbance caused by a cosmic particle strike to the combinational logic, also called a Single Event Transient, propagates to the input signal of the latch or flip flop during the critical transition period, then the latch or flip flop will store an incorrect data value and an SEU will occur.
Performance trends in the development of integrated circuits have lead to circuits with increasingly faster clock frequencies. Over a given time period, an increased clock frequency results in an increased number of critical transition periods. The increased number of critical transition periods per unit time provides increased opportunities for a cosmic ray induced voltage disturbance to cause a Single Event Upset by arriving at the latch or flip flop input during the edge of the clock signal. As a result of more frequent critical transition periods, modern high speed integrated circuits have an increased risk of SEU due to the increased likelihood that a Single Event Transient will arrive at the latch or flip flop during the critical transition period surrounding the clock edge.
FIG. 1 illustrates an example of a prior art logic circuit 10, including a combinational logic block 110 and a latch 13. The combinational logic block 110 produces a data signal 12 representing some binary data value, either a logic `0` or a logic `1.` The logic value of the data signal 12 is provided to a latch data input terminal D for storage in the latch 13. The prior art logic circuit 10 uses a clock signal 132 and an inverted clock signal 134, where the inverted clock signal 134 is the logical complement of the clock signal 132. In addition, the clock signal 132 and the inverted clock signal 134 change state, or assert and dessert, simultaneously. For example, the clock signals are asserted when the clock signal 132 rises from a logical `0` to a logical `1` and the inverted clock signal 134 falls from a logical `1` to a logical `0`. In operation, when the clock signal 132 and the inverted clock signal 134 are asserted the binary value of the data signal 12 will be provided as an output signal 14 on an output terminal Q. When the clock signals 132 and 134 are deasserted, the latch 13 will store and maintain the value of the data signal 12 as the output signal 14 until the clock signals 132 and 134 are again asserted. The period of time in which the clock signal 132 and the inverted clock signal 134 change state is also known as the clock signal transition.
FIG. 3 illustrates the timing relationship for the prior art logic circuit 10 under normal conditions when no cosmic ray has struck the combinational logic block 110. The reference numerals are used to identify these waveforms as the corresponding signal lines in FIG. 1. As illustrated, the data signal 12 from the combinational logic block 110 changes from a logic `1` to a logic `0` at some time well before the clock signal 132 and the inverted clock signal 134 are deasserted. When the clock signal transition occurs, the data signal 12 is in a stable logic `0` state. The binary value or state of the data signal 12 is stored in the latch 13 and is maintained as the output signal 14 at the output terminal Q when the clock signals 132 and 134 are deasserted. The `0` state is maintained on the output signal 14 even though the data signal 12 changes to a logic `1` state after the clock signal 132 and the inverted clock signal 134 have deasserted.
FIG. 4 shows the timing relationship for the prior art logic circuit 10 during a single event upset or SEU. The timing diagram of FIG. 4 includes a period of time when a cosmic ray strikes the combinational logic block 110 during the clock signal transition. The particle hit results in a transient disturbance 20 within the data signal 12'. The transient disturbance 20 causes the binary value of the data signal 12' to temporarily and erroneously change state. In the exemplary timing diagram of FIG. 4, the data signal 12' changes from a logic `0`, representing the value provided by the combinational logic block 110, to a logic `1`, representing the transient disturbance 20 caused by the cosmic particle strike.
The transient disturbance 20 within the data signal 12' propagates to the input terminal D of the latch 13. The latch 13 behaves as though the transient disturbance 20 is a valid input and changes state to a logic `1` resulting in an error 22 within the output signal 14'. As a result, the output signal 14' including the error 22 does not accurately represent the value of the data signal 12' provided by the combinational logic block 110. By the time the transient disturbance 20 has passed and the data signal 12' returns to the correct logic `0` state, the clock signals 132 and 134 have deasserted, thereby preventing the latch 13 from changing state until the next clock signal transition. As a result, an SEU occurs since the latch 13 stores and the output signal 14' maintains the error 22. Therefore, the example illustrated by FIG. 4 constitutes a single event upset.
In the past, four conventional techniques have been employed to provide SEU immunity for combinational logic. In the first conventional technique, the capacitance of all signal lines can be made very large so that a charge deposited by a cosmic ray does not cause a significant voltage disturbance. This approach is impractical for all but the most trivial integrated circuits because the resulting SEU immune combinational logic circuit is physically large, making it expensive, and either consumes excessive power or is very slow.
Second, all of the circuits that comprise a combinational logic block can be designed with a high current drive capability to remove any deposited charge very quickly and minimize any resulting voltage disturbance. This technique also leads to circuits that are physically large and consume excess power, and is impractical for most integrated circuits of interest.
A third conventional technique to reduce errors caused by cosmic ray strikes in combinational logic is known as "triple modular redundancy." In this technique, a combinational logic block can be replicated three times and a majority voting circuit used to ignore the incorrect data produced by any one block that is struck by a cosmic particle. Triple modular redundancy obviously increases size and power consumption of the circuit by at least a factor of three.
The fourth approach involves the use of special logic circuits in the combinational logic block, such as those described in U.S. Pat. No. 5,418,473 issued May 23, 1995 to John Canaris. That patent, entitled SINGLE EVENT UPSET IMMUNE LOGIC FAMILY, is incorporated in its entirety herein by reference. These special logic circuits are designed to recover from cosmic ray strikes without propagating a voltage transient. The disadvantage of this technique is that the special logic circuits are significantly different from those used in conventional integrated circuit design and are not compatible with common design tools and techniques.
Therefore, a need exists for an improved method of reducing or eliminating SEU caused by cosmic particle strikes in combinational logic. The improved method needs to be compatible with standard manufacturing processes and commonly used integrated circuit design tools and techniques. Further, what is needed is a technique for providing SEU immunity to combinational logic circuits without a large increase in the physical size of the circuit, without consuming excessive power and without requiring the age of unique logic circuits in the combinational logic.